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Authored by: Anonymous on Sunday, April 07 2013 @ 08:54 PM EDT |
I've seen this a number of times - an issued patent fully reads on a
pre-existing technology. It's not that the lawyer was trying to patent it - it's
just that they used such indistinct language that it applies there too.
Surely in such cases the patent is null and void. It clearly shows that the
patent author did not do an adequate prior art search, and the patent does not
disclose anything new.[ Reply to This | Parent | # ]
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- Well, ... - Authored by: Anonymous on Monday, April 08 2013 @ 01:20 AM EDT
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Authored by: Anonymous on Sunday, April 07 2013 @ 09:43 PM EDT |
It's like someone took the lid of a storage box and described
what he saw there-in .. :)[ Reply to This | Parent | # ]
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Authored by: Anonymous on Sunday, April 07 2013 @ 10:40 PM EDT |
Classic Raid
Commercial
A bit simplistic, but it would be nice if we could
spray something like this on
cockroaches like Parallel Iron, and they'd all
drop dead.
Waynehttp://madhatter.ca [ Reply to This | Parent | # ]
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Authored by: Jaywalk on Monday, April 08 2013 @ 12:11 PM EDT |
The patent specifically refers to memory. RAID checks for corrupted info on a
disk. This is the same thing, but with memory. Not that it's original. This
is the sort of thing Stratus and Tandem computers do; duplicate processing with
a checkpoint in between. In fact, I'm having a hard time seeing how they're
claiming it's comparable to Hadoop, which is a software system and this is
hardware. Stratus has been around since the '80s and Tandem since the '70s (HP
owns Tandem now). --- ===== Murphy's Law is recursive. ===== [ Reply to This | Parent | # ]
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Authored by: celtic_hackr on Tuesday, April 09 2013 @ 12:33 AM EDT |
This system had all that.
This mainframe computer, with multiple power supplies, multiple terminals,
multiple CPUs/per chip/per board, multiple memory systems, multiple storage
systems, multiple terminals.
It was all connected and fault tolerant.
This was in contracted prototype in 1990 and released in 1991. I worked on
building and unit testing these systems.
---------------------------------------------------
It should be noted that my IBM XT clone (which I still have the board of, and
still works) from 1990, has:
claim: one or more memory sections, including:
implemented by :(640k RAM plus upper memory sections)
claim: one or more memory devices having storage locations for storing data,
and
implemented by: (RAM memory, ROM memory, Floppy disks, harddrive, add-on 1MB
memory bd)
claim: a memory section controller capable of detecting faults in the memory
section and transmitting a fault message in response to the detected faults;
implemented by: BIOS, demonstrated very nicely at boot up as one of the memory
chips has gone bad. A very nice error message indicating which memory location
is at fault.
claim: one or more switches, including:
implemented by: physical memory selectable switches, and silicon control chips
on the motherboard.
claim: one or more interfaces for connecting to one or more external devices;
implemented by: 1MB additional memory on an external (to motherboard) add-on
board, ribbon cables for connecting disk drives, serial and parallel port
connectors, and I might even have a zipdrive board and device,
claim: a switch controller that executes software, including a routing
algorithm; and
implemented by:physical switches on the motherboard, BIOS, and DOS
claim: a selectively configurable switch fabric connected to one or more memory
sections and the one or more interfaces and interconnecting the memory sections
and the one or more interfaces based on the routing algorithm stored in the
switch controller; and
implemented by: AT&Ts 1915 crossbar switch (jk), The IBM Basic PROM, the
BIOS PROM, and control chips on the 1MB add-on card (at the least).
claim: a management system capable of receiving fault messages from the memory
section controllers and inactivating the memory section corresponding to the
fault message received by changing the routing algorithm, and wherein the
management system is further capable of determining and changing the routing
algorithm for use by the selectively configurable switch fabric in
interconnecting the memory sections and the one or more interfaces, providing
the determined routing algorithm to the switch controller, and instructing the
switch controller to execute the determined routing algorithm.
All handled by the BIOS.
======================================================
And THAT IS why those folks in the PTO are totally and completely UNQUALIFIED to
assess the patentability of software and computer related inventions.
Since my motherboard and the 1MB add-on boards are all older than 1992, I'd say
that's definitive prior art. I've never installed the add-on memory boards, and
don't know if they work. But, the MB powered up the last time I checked it,
which was a few years ago. It has, as I said a bad memory chip, and displays a
BIOS defined error message. It may halt at that point, or not. I can't remember.
Anyone think they can use any of that, let me know, PJ where to mail it all.
It's all in pieces and I may not have all the pieces to build an entire XT-Clone
system, It runs at 10.77 MHz.
P.S. I don't claim to have given an exhaustive list of parts of the XT system
that implement these claims. But these claims are so broad, it's hard to build
an exhaustive list. Well except for the "switch fabric" which is a
very stupid and incorrect way of saying "crossbar switch".
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